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Capgemini
As a DFT Lead Engineer, you will be responsible for architecting and implementing advanced Design-for-Test (DFT) techniques to ensure high-quality, testable SoC designs. You will work on Memory BIST, Scan Insertion, On-Chip Compression, Boundary Scan, Logic BIST, and Analog Testing across complex SoCs. This role demands strong expertise in ATPG vector generation, test mode implementation, and gate-level simulations with timing (SDF).
You will collaborate with cross-functional teams to resolve issues, drive innovation in DFT methodologies, and mentor junior engineers. A strong foundation in SoC design flow, excellent problem-solving skills, and hands-on experience with industry-standard ATPG and MBIST tools are essential.
What You’ll Love About Working Here:
We value flexibility and support our employees with remote work options and adaptable schedules to maintain a healthy work-life balance. Our inclusive culture brings together diverse professionals committed to growth, innovation, and excellence. You’ll have access to continuous learning opportunities and certifications in emerging technologies like cloud and AI.
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