Google

Silicon Networking Microarch and RTL Lead, Google Cloud

Posted On

March 11, 2025

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

March 27, 2025

Job Description

Lead a team of Engineers in the design organization to deliver complex IPs or Subsystems.
Own microarchitecture and implementation of complex IPs and subsystems in networking domain.
Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.
Identify and drive Power, Performance and Area improvements for the domains owned.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
5 years of experience in micro-architecture and design of IPs and Subsystems in networking domain such as packet processing, bandwidth management, congestion control etc.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

Experience with scripting languages (e.g., Python or Perl).
Experience in SoC designs and integration flows.
Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
5 years of experience in micro-architecture and design of IPs and Subsystems in networking domain such as packet processing, bandwidth management, congestion control etc.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be part of a team developing cutting-edge ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

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