Google

Silicon AI/ML Hardware Architect, Google Cloud

Posted On

March 4, 2025

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

March 20, 2025

Job Description

Evaluate different silicon solutions for executing Google’s data center AI accelerator roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Create high performance hardware/software interfaces.
Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Own microarchitecture of compute intensive IPs and subsystems.
Identify and drive power, performance, and area improvements for the modules owned.

Minimum qualifications:

Bachelor's degree in Electrical Engineering or equivalent practical experience.
5 years of experience in micro-architecture and design of graphics or ML IPs, handling Low Precision/Mixed Precision Numerics.
3 years of experience architecting networking ASICs from specification to production.
Experience developing Register Transfer Level (RTL) for Application-Specific Integrated Circuit (ASIC) subsystems using SystemVerilog.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

Experience in SoC designs and integration flows.
Experience working with software teams optimizing the hardware/software interface.
Experience estimating performance by analysis and modeling, and defining and driving performance test plans.
Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Proficiency in a procedural programming language (e.g., C++, Python, Go).

Bachelor's degree in Electrical Engineering or equivalent practical experience.
5 years of experience in micro-architecture and design of graphics or ML IPs, handling Low Precision/Mixed Precision Numerics.
3 years of experience architecting networking ASICs from specification to production.
Experience developing Register Transfer Level (RTL) for Application-Specific Integrated Circuit (ASIC) subsystems using SystemVerilog.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be part of a team developing AI accelerators in data centers and have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

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