Google

Silicon SoC Low Power Engineer, Front-End, Google Cloud

Posted On

Aug. 5, 2025

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

Aug. 21, 2025

Job Description

Participate in defining power management schemes and low power modes.
Create power specifications and Unified Power Format (UPF) definition for System on a Chip (SoC) and subsystems.
Estimate and track through all phases of the project.
Run power optimization tools, suggest ways to improve power and drive convergence.
Work with cross-functional teams for the delivery of power intent and power projections.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience in Application-Specific Integrated Circuit (ASIC) development, with power optimization.
Experience with low power schemes, power roll up, and power estimations.
Experience in ASIC design verification, synthesis, timing analysis.

Preferred qualifications:

Experience with coding languages (e.g., Python or Perl).
Experience in System on a Chip (SoC) designs and integration flows.
Experience with power optimization and power modeling tools.
Knowledge of high performance and low power design techniques.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience in Application-Specific Integrated Circuit (ASIC) development, with power optimization.
Experience with low power schemes, power roll up, and power estimations.
Experience in ASIC design verification, synthesis, timing analysis.

In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will also solve problems with micro-architecture and find solutions, and evaluate design options considering performance, power and area.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

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