Google

Chassis Power Architect, Silicon

Posted On

April 15, 2025

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

May 1, 2025

Job Description

Drive architecture and microarchitecture development for next generation power management controllers all the way from specification to SoC deployment.
Come up with Power optimization methods for various chassis IP’s.
Influence Power methodology for design, verification and implementation of deep submicron SoCs.
Develop innovative plans to achieve power optimization from circuit to system level.
Influence generic power management IPs to drive clock, reset, and power controls.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in power enhancement workflow and techniques.
Experience with power management IPs.

Preferred qualifications:

Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on chip power management IP design.
Experience in Verilog, SystemVerilog, RTL and gate-level SPICE simulations, and statistical SPICE models.
Experience using EDA tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
Experience in post-silicon power calibrations and debug.
Experience in design and analysis of full chip power with an understanding of clock, reset, and power sequencing interactions.

Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in power enhancement workflow and techniques.
Experience with power management IPs.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the Google Silicon Platform IP Architecture team, you will collaborate with SoC and IP hardware architects and Design Engineers to drive next generation power management controller and chassis power optimization in advanced technology nodes, focused on Google Tensor SoC and other associated products.

In this role, you will define power management controller and it’s deployment across SoC, power optimization methods, chart power roadmaps for Chassis IPs, propose power optimization plans in consultation with cross-functional teams, guide pre-silicon power modeling and post-silicon power correlation efforts, and interface with system and chipset power architects on both power planning and power management strategies. Your primary focus will be on our next-generation power management controller, chassis power architecture/microarchitecture and power vs performance tradeoffs for various SoC and chassis components.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

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