Memory Layout Design Engineer, Silicon
Job Description
- Collaborate with teams across Google Silicon to develop ideas for ASIC and hardware projects.
- Help setting design level Power, Performance, and Area goals for mobile SoC sub-systems.
- Work with Foundry, Technology, Architecture, Physical Design and Sign-off teams to understand requirements and constraints.
- Work with Implementation and Computer Aided Design (CAD) teams and make improvements to design quality.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 4 years of experience with layout design.
- Experience with library exchange format.
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience in coding and Unix shell scripting.
- Experience with Virtuoso XL and extraction tools such as Star-RC/QFS.
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 4 years of experience with layout design.
- Experience with library exchange format.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
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