Google

ASIC AI/ML Design Engineer, Silicon

Posted On

April 15, 2024

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

July 4, 2024

Job Description

Write microarchitecture and own RTL implementation of key components and features.
Engage with architects to align feature specifications.
Engage with Verification and Silicon Validation teams to ensure functionality of the design.
Provide input on synthesis, timing closure, and physical design of digital blocks.
Perform power, area, and performance trade-offs of digital designs and architectures. Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.

Minimum qualifications:

Bachelor’s degree in Electrical Engineering, Computer Science Engineering, or equivalent practical experience.
4 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
4 years experience in ARM-based SoCs, interconnects and ASIC methodology.

Preferred qualifications:

Master’s degree in Electrical Engineering or Computer Engineering.
4 years of experience with IP design for clocking, interconnects, and peripherals.
Experience in scripting language such as Python or Perl.
Experience with methodologies for low power estimation, timing closure, and synthesis.
Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

Bachelor’s degree in Electrical Engineering, Computer Science Engineering, or equivalent practical experience.
4 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
4 years experience in ARM-based SoCs, interconnects and ASIC methodology.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you will be part of a team that designs and builds the hardware and software that power all of Google's Pixel phones. Specifically, you will be part of the team which designs the Tensor Processing Unit (TPU), the heart of Google’s Pixel phones. You will be working with architects and engineers building industry leading AI/ML cores powering Google’s future Pixel phones. You'll own microarchitecture and design of digital logic using SystemVerilog and/or Chisel for the gChips TPU team. You will interface with architects to define features and interface with Physical Design teams to ensure efficient implementation to produce high-quality Power, Performance, and Area.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

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