Capgemini

ANALOG LAYOUT ENGINEER | 4 TO 6 YEARS| BENGALURU, COIMBATORE & HYDERABAD

Posted On

Sept. 19, 2024

Location

Coimbatore, Tamil Nadu

Experience Level

Experienced Professionals

Job Type

Permanent

Apply By

Oct. 9, 2024

Job Description

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Job Description

Experience in Mixed-Signal layout design, holding bachelor’s degree
To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications.
Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below.
Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.
Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must.
Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
Ability to understand design constraints and implement high-quality layouts.
Multiple Tape out support experience will be an added advantage.
Good people skills and critical thinking abilities to resolve the issue technically, and professionally.
Excellent communication. Responsible for timely execution with high quality of layout design.

Primary Skills

Analog Layout
Process or technology experience: TSMC – 7nm, 5nm, 10nm,28nm, 45nm,40nm
EDA Tools:
Layout Editor: Cadence Virtuoso L, XL
Physical verification: DRC, LVS, Calibre

Secondary Skills

IO layout

Job Description

Experience in Mixed-Signal layout design, holding bachelor’s degree
To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications.
Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below.
Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.
Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must.
Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
Ability to understand design constraints and implement high-quality layouts.
Multiple Tape out support experience will be an added advantage.
Good people skills and critical thinking abilities to resolve the issue technically, and professionally.
Excellent communication. Responsible for timely execution with high quality of layout design.

Primary Skills

Analog Layout
Process or technology experience: TSMC – 7nm, 5nm, 10nm,28nm, 45nm,40nm
EDA Tools:
Layout Editor: Cadence Virtuoso L, XL
Physical verification: DRC, LVS, Calibre

Secondary Skills

IO layout

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