ASIC RTL Design Engineer
Job Description
- Perform RTL development (SystemVerilog), debug functional/performance simulations.
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
- Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
- Communicate and work with multi-disciplined and multi-site teams.
Minimum qualifications:
- Bachelor’s degree in Electrical/Computer Engineering.
- Experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with a scripting language like Python or Perl.
- Experience with ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
- Master’s degree in Electrical/Computer Engineering.
- 3 years of experience with IP design for clocking, interconnects, peripherals.
- Experience with methodologies for low power estimation, timing closure, synthesis.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
- Bachelor’s degree in Electrical/Computer Engineering.
- Experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience with a scripting language like Python or Perl.
- Experience with ARM-based SoCs, interconnects and ASIC methodology.
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