Google

Silicon Networking RTL Design Engineer

Posted On

April 15, 2025

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

May 1, 2025

Job Description

Own Register-Transfer Level (RTL) implementation of Internet Protocols (IPs) and subsystems in Networking domain.
Work with design team members to close feature definitions and develop micro-architecture specifications.
Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Work on Power, Performance and Area improvements for the domains owned.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).
Experience in micro-architecture and design of Internet Protocols (IPs) and Subsystems.
Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

Experience in Networking domain like Packet processing, bandwidth management, congestion control, etc.
Experience with scripting languages (e.g., Python or Perl).
Knowledge of bus architectures, fabrics, processor design, or memory hierarchies.
Knowledge of high performance and low power design techniques.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).
Experience in micro-architecture and design of Internet Protocols (IPs) and Subsystems.
Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

You will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical solutions, and evaluate design options with performance, power and area.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

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